library ieee;
use ieee.std_logic_1164.all;
use WORK.constants.all;

entity REG32 is
	port (
		data_in		:	in std_logic_vector(DATA_SIZE-1 downto 0);
		data_out	:	out std_logic_vector(DATA_SIZE-1 downto 0);
		we			:	in std_logic;
		clk			:	in std_logic;
		reset		:	in std_logic
	);
end REG32;

architecture BEHAVIORAL of REG32 is
	signal Q_temp : std_logic_vector(DATA_SIZE-1 downto 0) := (others => '0');
begin
	P_REG32 : process(clk, reset, we)
	begin
		if reset = '1' then
			Q_temp <= (Q_temp'range => '0');
		elsif clk'event and clk = '0' then
			if we = '1' then
				Q_temp <= data_in;
			end if;
		end if;
	end process;
	data_out <= Q_temp;
end;
